1. Field of the Invention
The invention generally relates to the testing of circuits provided in semiconductor integrated circuits or printed boards, and more particularly, to a register circuit for scan path testing to reduce the required time for testing under a serial scan method.
2. Description of the Related Art
Scanning methods are available for the purpose of testing circuits provided in semiconductor integrated circuit or printed boards. The scanning methods include a serial scan method and a parallel scan method. Under the serial scan method, a continuous shift register is previously provided within the circuit whereby that shift register will be externally accessed at the time of testing. By access to the shift register, test data may be applied to the desired circuit portion to be tested within the circuit, and/or data indicating the processing result from the circuit portion to be tested may be externally provided via the shift register.
In general, hundreds to thousands of test data are applied to the circuit to be tested in order to determine whether the circuit to be tested is normal or not, with test data indicating the test result provided for each applied test data. In the above-mentioned serial scan method, the input and output of test data are performed serially by a clock signal, causing an increase in the total time required for testing as the number of test data, i.e., the number of testing increases.
FIG. 5 is a block diagram showing a semiconductor integrated circuit (or a printed board) comprising the circuits to be tested. Referring to FIG. 5, a semiconductor integrated circuit 100 comprises circuit portions to be tested (under-test circuits) 20, 40 and 60, other circuit portions which do not require testing 30 and 50, and shift register cells 1-10 for implementing serial scan path testing. The desired circuit is formed by the combination of each circuit portion 20, 30, 40, 50 and 60. Registers formed of cells 1-10 implement the shift register at the time of testing by the serial scan method. During normal operation, plural registers formed by cells 1-3, 4-5, 6-7 and 8-10 are used as the required registers for transferring signals between circuit portions 20-60. Therefore, these cells 1-10 are used as a shift register for testing before shipment of IC 100 from the factory, while being used as registers for normal operation by users after shipment.
FIG. 6 is circuit diagram of a conventional cell 1b. Referring to FIG. 6, the cell 1b comprises a selector 11 responsive to a shift control signal SHF for selecting either a scan input SIN or a data input DIN, and a D-type flip flop 12 operative in response to clock signal CLK. The output data Q from the flip flop 12 is applied to a scan output SOUT and a data output DOUT. In order to constitute the shift register of FIG. 5 using a plurality of cells b as shown in FIG. 6, the cells 1-10 are cascaded via the scan input SIN and the scan output SOUT of each cell 1b. When the cell 1b is to be used as an independent data holding circuit, the cell 1b is connected to another circuit via the data input DIN and the data output DOUT. The selector 11 responds to a shift control signal SHF to selectively provide data applied to either the scan input SIN or the data input DIN to the flip flop 12.
FIG. 7 is a circuit connection diagram showing the connection of the cell 1b shown in FIG. 6 in a semiconductor integrated circuit. Referring to FIG. 7, three cells 1b, 2b and 3b connect between a circuit to be tested 20 and another circuit 30 as shown. Cell 1b is the circuit configuration shown in FIG. 6. The other cells 2b and 3b also have a similar circuit configuration. For the implementation of the serial scan path the scan output SOUT of the cell 1b is connected to the scan input SIN of the cell 2b. The connection between cells 2b and 3b are also provided in the likewise manner. Each of cells 1b, 2b and 3b has each data input DIN connected so as to receive data from the circuit to be tested 20, and its data output DOUT connected to the other circuit 30. Although not shown, the other cells 4-10 in a semiconductor integrated circuit 100 according to FIGS. 5 and 6 are connected in a likewise manner shown in the circuit of FIG. 7.
Now, the operation of a circuit having cells according to FIG. 6 will be described. In the following description, it is assumed that the circuit portions 20, 40 and 60 of FIG. 5 need be tested but circuit portions 30 and 50 do not need to be tested. First, a shift control signal SHF is applied to each of cells 1-10. The selector 11 provided in each of cells 1-10 responds to the signal SHF for providing the data applied to the scan input SIN to the flip flop 12. As a result, a shift register is configured by shift cells 1-10. Test data is inputted via the configured shift register. After test data is inputted, each circuit portion 20-60 is operated. Following the operation, the data indicating the result of the test is provided to cells 1-7. Since cells 8-10 are not connected to the circuits to be tested, data indicating the result of the test will not be provided to these cells. The data indicating the result of the test held in each cell 1-7 respond to a clock signal CLK to be outputted from the configured shift register.